Look-up Processor for Ipv4/ipv6 Packet Classification

This paper deals with design and implementation of Look-up processor which performs IPv4 and IPv6 packet classification on the basis of configurable rules. They can be specific e.g. for routing, filtering or attack detection so the target usage of the processor results from their selection. The origin intention is to use it in PC-based router which is being developed under the Liberouter project [1]. The proposed architecture enables achieving multigigabit speed. Its design was implemented in VHDL language and the target technology is FPGA.